Digital RF processing: Toward low-cost reconfigurable radios

RF circuits for multi-gigahertz frequencies have recently migrated to state-of-the-art low-cost digital CMOS processes. This article visits fundamental techniques recently developed that migrate RF and analog design complexity to the digital domain for a wireless RF transceiver. All-digital phase locked loop and direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. Software layers are defined to enable these architectures to develop an efficient software-defined radio. The ideas presented have been used to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio.