On the Design of Low-Power Cache Memories for Homogeneous Multi-Core Processors

被引：3
|
作者：
Asaduzzaman, Abu [1 ]
Rani, Manira [2 ]
Sibai, Fadi N. [3 ]
机构：
[1] Wichita State Univ, Dept Elect Eng & Comp Sci, Wichita, KS 67260 USA
[2] Florida Atlantic Univ, Dept Comp & Elect Eng, Dept Comp Sci, Boca Raton, FL 33431 USA
[3] UAE Univ, Fac IT, Comp Syst Design, Al Ain, U Arab Emirates
来源：
2010 INTERNATIONAL CONFERENCE ON MICROELECTRONICS | 2010年
关键词：
Cache memory organization; homogeneous systems; low-power design; multi-core processor;
D O I：
10.1109/ICM.2010.5696168
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We investigate the impact of level-1 cache (CL1) parameters, level-2 cache (CL2) parameters, and cache organizations on the power consumption and performance of multi-core systems. We simulate two 4-core architectures - both with private CL1s, but one with shared CL2 and the other one with private CL2s. Simulation results with MPEG4, H.264, matrix inversion, and DFT workloads show that reductions in total power consumption and mean delay per task of up to 42% and 48%, respectively, are possible with optimized CL1s and CL2s. Total power consumption and the mean delay per task depend significantly on the applications including the code size and locality.
引用
收藏
页码：387 / 390
页数：4
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