A Robust Architecture for Post-Silicon Skew Tuning

被引:0
|
作者
Kao, Mac Y. C. [1 ]
Tsai, Kun-Ting [1 ]
Chang, Shih-Chieh [1 ]
机构
[1] Natl Tsing Hua Univ, Dept Comp Sci, Hsinchu 30043, Taiwan
来源
2011 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) | 2011年
关键词
Post-Silicon Tuning; Adjustable Delay Buffer; Phase Detector;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Clock skew minimization is important in VLSI design field. Due to the presence of Process, Voltage, and Temperature (PVT) variations, the Post-Silicon Skew Tuning (PST) technique with the ability of tolerating PVT variations has brought a broad discussion. A PST architecture can dynamically minimize the clock skew even after a chip is manufactured. However, testing the variation tolerance ability of a PST architecture is very difficult because the clock skew does not directly affect the functionality of a design. In addition, creating PVT variation in the traditional testing environment is not easy. Unlike most previous works which focus on the implementation and the performance issues of a PST architecture, the objective of this paper is to propose efficient test mechanisms and verify the variation tolerance ability. In addition, we also propose a novel structure to increase the robustness of a PST architecture in case of a manufacturing fault. Our experiment shows that with little overhead, we can achieve robustness.
引用
收藏
页码:774 / 778
页数:5
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