A Robust Architecture for Post-Silicon Skew Tuning

被引:0
|
作者
Kao, Mac Y. C. [1 ]
Tsai, Kun-Ting [1 ]
Chang, Shih-Chieh [1 ]
机构
[1] Natl Tsing Hua Univ, Dept Comp Sci, Hsinchu 30043, Taiwan
来源
2011 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) | 2011年
关键词
Post-Silicon Tuning; Adjustable Delay Buffer; Phase Detector;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Clock skew minimization is important in VLSI design field. Due to the presence of Process, Voltage, and Temperature (PVT) variations, the Post-Silicon Skew Tuning (PST) technique with the ability of tolerating PVT variations has brought a broad discussion. A PST architecture can dynamically minimize the clock skew even after a chip is manufactured. However, testing the variation tolerance ability of a PST architecture is very difficult because the clock skew does not directly affect the functionality of a design. In addition, creating PVT variation in the traditional testing environment is not easy. Unlike most previous works which focus on the implementation and the performance issues of a PST architecture, the objective of this paper is to propose efficient test mechanisms and verify the variation tolerance ability. In addition, we also propose a novel structure to increase the robustness of a PST architecture in case of a manufacturing fault. Our experiment shows that with little overhead, we can achieve robustness.
引用
收藏
页码:774 / 778
页数:5
相关论文
共 50 条
  • [31] A Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning
    Lak, Zahra
    Nicolici, Nicola
    IEEE TRANSACTIONS ON COMPUTERS, 2014, 63 (05) : 1074 - 1084
  • [32] Efficient Router Architecture for Trace Reduction During NoC Post-Silicon Validation
    Rout, Sidhartha Sankar
    Patil, Suyog Bhimrao
    Chaudhari, Vaibhav Ishwarlal
    Deb, Sujay
    32ND IEEE INTERNATIONAL SYSTEM ON CHIP CONFERENCE (IEEE SOCC 2019), 2019, : 230 - 235
  • [33] A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning
    Kimura, Shuta
    Hashimoto, Masanori
    Onoye, Takao
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2012, E95A (12) : 2292 - 2300
  • [34] Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation
    Daoud, Ehab Anis
    Nicolici, Nicola
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (04) : 559 - 570
  • [35] Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements
    Li, Bing
    Schlichtmann, Ulf
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (11) : 1784 - 1797
  • [36] Optimizing Post-silicon Conformance Checking
    Lei, Li
    Cong, Kai
    Xie, Fei
    2013 IEEE 31ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2013, : 499 - 502
  • [37] On Signal Tracing in Post-Silicon Validation
    Xu, Qiang
    Liu, Xiao
    2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, : 259 - 264
  • [38] A STATISTICALLY ROBUST METHODOLOGY FOR OPTIMIZED SAMPLE SIZE DETERMINATION FOR FPGA POST-SILICON VALIDATION
    Qin, Weijun
    2017 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC 2017), 2017,
  • [39] Automating post-silicon debugging and repair
    Chang, Kai-Hui
    Markov, Igor L.
    Bertacco, Valeria
    IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2, 2007, : 91 - 98
  • [40] Post-Silicon Validation, Debug and Diagnosis
    Mishra, Prabhat
    Fujita, Masahiro
    Singh, Virendra
    Tamarapalli, Nagesh
    Kumar, Sharad
    Mittal, Rajesh
    2013 26TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2013 12TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID), 2013, : LXIII - LXV