SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level Synthesis

被引：24
作者：
Yasin, Muhammad [1 ]
Zhao, Chongzhi [1 ]
Rajendran, Jeyavijayan [1 ]
机构：
[1] Texas A&M Univ, Dept Elect & Comp Engn, College Stn, TX 77843 USA
来源：
2019 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) | 2019年
基金：
美国国家科学基金会;
关键词：
D O I：
10.1109/iccad45719.2019.8942150
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Logic locking has emerged as a promising countermeasure against piracy and reverse engineering attacks on integrated circuits. The state-of-the-art logic locking techniques, more specifically stripped-functionality logic locking (SFLL), offer provable security guarantees against many attacks. However, these techniques focus on protecting individual modules or even parts of a module, failing to deliver system-wide security. This paper sheds light on integrating logic locking with high-level synthesis (HLS) in an attempt to deliver system-wide security. We demonstrate the integration of SFLL with LegUp HLS tool for an image processing application.
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页数：4
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