Sequential logic asynchronous design for CMOS implementation

被引：0
作者：
Lemberski, I [1 ]
机构：
[1] Riga Aviat Univ, LV-1019 Riga, Latvia
来源：
MELECON '98 - 9TH MEDITERRANEAN ELECTROTECHNICAL CONFERENCE, VOLS 1 AND 2 | 1998年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
The method [6] of hazard elimination is adapted for CMOS circuit design. Tt is shown opportunity of hazard-free ee CMOS implementation with input inverters. Input variable hazards are avoided by changing one input variable at the time and internal variable hazards - by neighbouring or Tracey's assignment. The main attention is focused on avoiding hazards between input and internal variables. The internal state assignment to avoid errors caused by this type of hazards is offered.
引用
收藏
页码：613 / 616
页数：4
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