Sequential logic asynchronous design for CMOS implementation

被引：0
作者：
Lemberski, I [1 ]
机构：
[1] Riga Aviat Univ, LV-1019 Riga, Latvia
来源：
MELECON '98 - 9TH MEDITERRANEAN ELECTROTECHNICAL CONFERENCE, VOLS 1 AND 2 | 1998年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
The method [6] of hazard elimination is adapted for CMOS circuit design. Tt is shown opportunity of hazard-free ee CMOS implementation with input inverters. Input variable hazards are avoided by changing one input variable at the time and internal variable hazards - by neighbouring or Tracey's assignment. The main attention is focused on avoiding hazards between input and internal variables. The internal state assignment to avoid errors caused by this type of hazards is offered.
引用
收藏
页码：613 / 616
页数：4
相关论文
共 50 条
[21]   Asynchronous Logic Implementation Based on Factorized DIMS [J].
Lemberski, Igor .
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2017, 26 (05)
[22]   Asynchronous ACS design in CMOS VLSI [J].
Zhao, Bing ;
Hei, Yong ;
Qiu, Yulin .
Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics, 2004, 24 (01) :98-102
[23]   FAULT EFFECTS IN ASYNCHRONOUS SEQUENTIAL LOGIC-CIRCUITS [J].
SHIEH, MD ;
WEY, CL ;
FISHER, PD .
IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1993, 140 (06) :327-332
[24]   Design and Implementation of 8-Bit Vedic Multiplier Using CMOS Logic [J].
Deodhe, Yeshwant ;
Kakde, Sandeep ;
Deshmukh, Rushikesh .
2013 INTERNATIONAL CONFERENCE ON MACHINE INTELLIGENCE AND RESEARCH ADVANCEMENT (ICMIRA 2013), 2013, :340-344
[25]   CMOS MULTIPLE-VALUED LOGIC DESIGN .1. CIRCUIT IMPLEMENTATION [J].
JAIN, AK ;
BOLTON, RJ ;
ABDELBARR, MH .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 1993, 40 (08) :503-514
[26]   Power Aware Design and Implementation of 8-bit Asynchronous Arithmetic and Logic Unit [J].
Singh, Hardeep .
2009 IEEE INTERNATIONAL ADVANCE COMPUTING CONFERENCE, VOLS 1-3, 2009, :1037-1047
[27]   DESIGN OF ASYNCHRONOUS MULTILEVEL SEQUENTIAL CIRCUITS [J].
DUNCAN, FG ;
ZISSOS, D .
PROCEEDINGS OF THE INSTITUTION OF ELECTRICAL ENGINEERS-LONDON, 1972, 119 (02) :133-&
[28]   ADVANCED ASPECTS OF ASYNCHRONOUS LOGIC DESIGN [J].
LEWIN, DW .
COMPUTER JOURNAL, 1971, 14 (03) :254-+
[29]   Asynchronous Logic Design Targeting LUTs [J].
Lemberski, Igor ;
Suponenkovs, Artjoms .
2018 7TH MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING (MECO), 2018, :420-425
[30]   A NEW APPROACH TO DESIGN OF ASYNCHRONOUS LOGIC [J].
LEWIN, DW .
RADIO AND ELECTRONIC ENGINEER, 1968, 36 (06) :327-&
12345