An Energy-Efficient Deep Reinforcement Learning Accelerator With Transposable PE Array and Experience Compression

被引：6

作者：

Kim, Changhyeon ^{[1
]}

Kang, Sanghoon ^{[1
]}

Choi, Sungpill ^{[1
]}

Shin, Dongjoo ^{[1
]}

Kim, Youngwoo ^{[1
]}

Yoo, Hoi-Jun ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Sch Elect Engn, Daejeon 34141, South Korea

来源：

IEEE SOLID-STATE CIRCUITS LETTERS | 2019年 / 2卷 / 11期

关键词：

Deep learning ASIC; deep learning; deep neural network; mobile deep learning; reinforcement learning;

D O I：

10.1109/LSSC.2019.2941252

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this letter, we propose a low power deep reinforcement learning (DRL) SoC, supporting CNN and learning-optimized RNN, and fully connected layer. The adaptive reuse of weights and inputs, and data encoding/decoding techniques reduces power consumption and peak memory bandwidth of DRL processing by 31% and 41%, respectively. The 65-nm 16-mm(2) chip achieves a peak 2.16 TFLOPS/W at 0.73 V and 204 GFLOPS at 1.1 V with 16-bit data.

引用

页码：228 / 231

页数：4

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