Optimization of double metal-gate InAs/Si heterojunction nanowire TFET

被引：9
作者：
Choi, Yejoo [1 ]
Hong, Yuri [1 ]
Ko, Eunah [2 ]
Shin, Changhwan [1 ]
机构：
[1] Sungkyunkwan Univ, Elect & Comp Engn, Suwon, South Korea
[2] Univ Michigan, Elect Engn & Comp Sci, Ann Arbor, MI 48109 USA
来源：
SEMICONDUCTOR SCIENCE AND TECHNOLOGY | 2020年 / 35卷 / 07期
基金：
新加坡国家研究基金会;
关键词：
work function engineering; heterojunction double metal-gate tunnel field effect transistor; interface traps; TUNNEL; SIMULATION; IMPACT;
D O I：
10.1088/1361-6641/ab8b1f
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The performance of a double metal-gate (DG) InAs/Si heterojunction gate-all-around vertical nanowire tunnel field effect transistor ( FEET) is studied using a technology-computer-aided-design tool. Typical drawbacks of the conventional 11-ET are resolved by taking advantage of using (i) InAs source and (ii) DG structure. The InAs is used as a source material to address the low on-state drive current in the TEST. In addition, a double metal-gate structure is adopted to control the ambipolar current by optimizing the work function of metal gates. Furthermore, the effect of fabrication-induced interface traps at InAs/Si and Si/HfO2 on device performance is studied. Predictive simulations with various interface traps indicate that a steep subthreshold slope is achieved for D-it >= 10(13) cm(-2) eV(-1) at the InAs/Si interface. To further analyze the optimized device, DC and AC analysis is done for the optimized TEST with traps.
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页数：7
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