Power Characteristics of Asynchronous Networks-on-Chip

被引:0
|
作者
Rashed, Maher [1 ]
Abd El Ghany, Mohamed A. [2 ]
Ismail, Mohammed [3 ,4 ]
机构
[1] German Univ Cairo, Dept Commun Engn, Cairo, Egypt
[2] Cairo Univ, Dept Elect Engn, Cairo, Egypt
[3] Ohio State Univ, Elect & Comp Engn Dept, Columbus, OH 43210 USA
[4] KTH, The RaMSiS Grp, Stockholm, Sweden
关键词
NoC; GALS; Power Dissipation; Interswitch Links; SYSTEMS;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Power characteristics of different Asynchronous Network on Chip (NoC) architectures are developed. Among different NoC architectures, the Butterfly Fat Tree (BFT) dissipates the minimum power. With increasing the number of IP blocks, the relative power consumption of the interconnects and the associate repeaters of the Asynchronous NoC architecture decreases as compared to the power consumption of the network switches. The power dissipation of the Asynchronous architecture is decreased by up to 57% as compared to the power dissipation of the conventional Synchronous architecture. The BFT is more efficient with increasing the number of IP blocks.
引用
收藏
页码:160 / 165
页数:6
相关论文
共 50 条
  • [21] Area and Laser Power Scalability Analysis in Photonic Networks-on-Chip
    Abadal, Sergi
    Cabellos-Aparicio, Albert
    Lazaro, Jose A.
    Nemirovsky, Mario
    Alarcon, Eduard
    Sole-Pareta, Josep
    2013 17TH INTERNATIONAL CONFERENCE ON OPTICAL NETWORKING DESIGN AND MODELING (ONDM), 2013, : 131 - 136
  • [22] Wormhole Computing in Networks-on-Chip
    Rettkowski, Jens
    Goehringer, Diana
    2021 31ST INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL 2021), 2021, : 273 - 274
  • [23] Approximate Wireless Networks-on-Chip
    Ascia, Giuseppe
    Catania, Vincenzo
    Monteleone, Salvatore
    Palesi, Maurizio
    Patti, Davide
    Jose, John
    2018 XXXIII CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS), 2018,
  • [24] Communication models in networks-on-chip
    Carara, Everton
    Mello, Aline
    Moraes, Fernando
    RSP 2007: 18TH IEEE/IFIP INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS, 2007, : 57 - +
  • [25] On the Capacity of Bufferless Networks-on-Chip
    Shpiner, Alexander
    Kantor, Erez
    Li, Pu
    Cidon, Israel
    Keslassy, Isaac
    IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2015, 26 (02) : 492 - 506
  • [26] On the Capacity of Bufferless Networks-on-Chip
    Shpiner, Alexander
    Kantor, Erez
    Li, Pu
    Cidon, Israel
    Keslassy, Isaac
    2012 50TH ANNUAL ALLERTON CONFERENCE ON COMMUNICATION, CONTROL, AND COMPUTING (ALLERTON), 2012, : 770 - 777
  • [27] Statistical Approach to Networks-on-Chip
    Cohen, Itamar
    Rottenstreich, Ori
    Keslassy, Isaac
    IEEE TRANSACTIONS ON COMPUTERS, 2010, 59 (06) : 748 - 761
  • [28] eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip
    Beldachi, Arash Farhadi
    Hollis, Simon
    Nunez-Yanez, Jose L.
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2014, 8 (03): : 148 - 162
  • [29] Power Characteristics of Networks on Chip
    Abd El Ghany, Mohamed A.
    El-Moursy, Magdy A.
    Korzec, Darek
    Ismail, Mohammed
    2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 3721 - 3724
  • [30] Evaluating the impact of data encoding techniques on the power consumption in networks-on-chip
    Palma, Jose C. S.
    Indrusiak, Leandro Soares
    Moraes, Fernando G.
    Ortiz, Alberto Garcia
    Glesner, Manfred
    Reis, Ricardo A. L.
    IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2006, : 426 - +