An SEU Hardened 65nm/4T-SRAM Cell for High Reliable Space Applications

A novel mono-stable 4T-SRAM cell is proposed in this paper. The cell is designed in 65nm LPCMOS process and simulated to find out the linear energy transfer threshold of SEU. T-CAD simulation results show that its LETth for data(1) is up to 41.6 MeV/mg/cm(2), almost the same as DICE, and the data error rate can be reduce to 1.2x10(-11)/bit. day with a particular duplication redundancy SRAM structure. The proposed 4T cell takes advantage of small cell size and solid anit-SEU ability, showing good potential to be used in SEU hardened SRAM.