A high-speed sense-amplifier based flip-flop

被引：0
|
作者：
De Caro, D [1 ]
Napoli, E [1 ]
Petra, N [1 ]
Strollo, AGM [1 ]
机构：
[1] Univ Naples Federico II, Dept Elect & Telecom, Naples, Italy
来源：
PROCEEDINGS OF THE 2005 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOL 2 | 2005年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The paper presents a new sense-amplifier based flip-flop. The output latch of proposed circuit can be considered as an hybrid solution between the standard NAND based SR latch and the N-(CMOS)-M-2 approach. New solution provides ratioless design, reduced short circuit power dissipation and glitch free operation. Proposed flip-flop, designed for a 0.25 mu m technology, exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops.
引用
收藏
页码：II99 / II102
页数：4
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