An all-digital fast-locking programmable DLL-based clock generator

被引：24

作者：

Liang, Chuan-Kang ^{[1
,2
]}

Yang, Rong-Jyi ^{[1
,2
]}

Liu, Shen-Luan ^{[1
,2
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan

[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10617, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2008年 / 55卷 / 01期

关键词：

all-digital delay-locked loop (DLL); clock generator; clock multiplier; fast-locking; frequency synthesizer;

D O I：

10.1109/TCSI.2007.913612

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An all-digital fast-locking programmable DLL-based clock generator is presented. By resetting the output clock every two input clock periods, the initial minimal delay constraint in the conventional architecture is eliminated. Compared with the previous work, the short locking time is also achieved. The proposed circuit has been fabricated in 0.35-mu m CMOS process and occupies the active area of 0.216 mm(2). The clock multiplication ratio is programmed from 2 to 15. The frequency ranges of the input and output clocks are 4 similar to 200 MHz and 60 similar to 450 MHz, respectively. It dissipates less than 17 mW at all operating frequencies from a 3.3-V supply.

引用

页码：349 / 357

页数：9

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