3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

被引：47

作者：

Civale, Yann ^{[1
]}

Tezcan, Deniz Sabuncuoglu ^{[1
]}

Philipsen, Harold G. G. ^{[1
]}

Duval, Fabrice F. C. ^{[2
]}

Jaenen, Patrick ^{[2
]}

Travaly, Youssef ^{[1
]}

Soussan, Philippe ^{[1
]}

Swinnen, Bart ^{[1
]}

Beyne, Eric ^{[3
]}

机构：

[1] Interuniv Microelect Ctr, Interconnect & Packaging Dept, B-3001 Louvain, Belgium

[2] Interuniv Microelect Ctr, Dept Lithog, B-3001 Louvain, Belgium

[3] Interuniv Microelect Ctr, Proc Technol Dept, B-3001 Louvain, Belgium

来源：

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2011年 / 1卷 / 06期

关键词：

Integrated circuit fabrication; integrated circuit interconnections; integrated circuit packaging; integrated circuits; packaging;

D O I：

10.1109/TCPMT.2011.2125791

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

In this paper, we report on the processing and the electrical characterization of a 3-D-wafer level packaging through-silicon-via (TSV) flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn micro-bump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50 mu m. The actual TSV and micro-bump process uses 3 masks, two Si-deep-reactive ion etching steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35 mu m (TSV)-T-phi, 5 mu m thick polymer liner, 25-mu m-phi Cu TSV, 50 mu m deep TSV, and a 60 mu m TSV pitch.

引用

页码：833 / 840

页数：8

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