An efficient high speed AES implementation using Traditional FPGA and LabVIEW FPGA platforms

The LabVIEW FPGA platform is based on graphical programming approach, which makes easy the FPGA programming and the I/O interfacing. The LabVIEW FPGA significantly improves the design productivity and helps to reduce the time to market. On the other hand, traditional FPGA platform is helpful to get an efficient/optimized design by providing control over each bit using HDL programming languages. This work utilized traditional as well as LabVIEW FPGA platforms to get an optimized high speed design of AES (Advanced Encryption Standard). The AES is considered to be a secure and reliable cryptographic algorithm that is used worldwide to provide encryption services, which hide the information during communication over untrusted networks, like Internet. Here, AES core is proposed to secure the communication between ROV (Remotely Operated Vehicle) and control station in a marine environment; but this core can be fit in any other high speed electronic communications. This work provides encryption of 128-bytes, 256-bytes and 512-bytes set of inputs (individually and simultaneously) using a 128-bit key. In case of simultaneous implementation, all the above mentioned set of inputs is encrypted in parallel. This simultaneous implementation is resulted in throughput of Gbps range.