An algorithmic of analog-to-digital converter using current-mode and digital CMOS process

被引：0
作者：
Oki, N [1 ]
机构：
[1] UNESP, FEIS, DEE, Sao Paulo, Brazil
来源：
1998 MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS | 1999年
关键词：
D O I：
10.1109/MWSCAS.1998.759544
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper a new algorithmic of Analog-to-Digital Converter is presented. This new topology use the current-mode technique that allows a large dynamic range and can be implemented in digital CMOS process. The ADC proposed is very small and can handle high sampling rates. Simulation results using a 1.2um CMOS process show that an 8-b ADC can support a sampling rate of 50MHz.
引用
收藏
页码：520 / 521
页数：2
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