Low power and high performance dynamic CMOS XOR/XNOR gate design

被引：19

作者：

Wang, Jinhui ^{[1
,2
]}

Gong, Na ^{[3
]}

Hou, Ligang ^{[1
,2
]}

Peng, Xiaohong ^{[1
,2
]}

Geng, Shuqin ^{[1
,2
]}

Wu, Wuchen ^{[1
,2
]}

机构：

[1] Beijing Univ Technol, VLSI, Beijing, Peoples R China

[2] Beijing Univ Technol, Syst Lab, Beijing, Peoples R China

[3] SUNY Buffalo, Dept Comp Sci & Engn, Buffalo, NY 14260 USA

来源：

MICROELECTRONIC ENGINEERING | 2011年 / 88卷 / 08期

基金：

中国国家自然科学基金;

关键词：

Dynamic XOR/XNOR Gate; Leakage; Power; Variation; LEAKAGE CURRENT;

D O I：

10.1016/j.mee.2011.02.068

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A hybrid network technique is proposed in dynamic CMOS XOR/XNOR gate to reduce the power consumption, save the layout area and avoid signal skew. Compared to the standard N type dynamic gate with similar delay time, the leakage power, dynamic power and layout area of the novel XOR/XNOR gate are reduced by up to 51%, 13% and 24%, respectively. Also, the inputs and clock signals combination static state dependent leakage characteristics of three dynamic CMOS XOR/XNOR gates are analyzed thoroughly. Finally, their robustness to noise, process and temperature variations are discussed. (C) 2011 Elsevier B.V. All rights reserved.

引用

页码：2781 / 2784

页数：4

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