A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

被引：146

作者：

Zhang, K ^{[1
]}

Bhattacharya, U ^{[1
]}

Chen, ZP ^{[1
]}

Hamzaoglu, F ^{[1
]}

Murray, D ^{[1
]}

Vallepalli, N ^{[1
]}

Wang, Y ^{[1
]}

Zheng, B ^{[1
]}

Bohr, M ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2006年 / 41卷 / 01期

关键词：

dynamic power supply; MOS memory integrated circuits; SPAM cell; static noise margin (SNNI); static random-access memory (SRAM); write margin;

D O I：

10.1109/JSSC.2005.859025

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high-performance 65-nm CMOS technology. The fully synchronized design achieves a 3-GHz operating frequency at 1.1-V power supply. The power supply at SRAM cell array is dynamically switched between two different voltage levels during READ and WRITE operations. Silicon measurement has proven this method to be effective in achieving both good cell READ and WRITE margins, while lowering the overall SRAM leakage power consumption.

引用

页码：146 / 151

页数：6

共 6 条

[1]

[Anonymous], 2004, INT TECHNOLOGY ROADM

[2] A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm2 SRAM cell [J].

Bai, P ;

Auth, C ;

Balakrishnan, S ;

Bost, M ;

Brain, R ;

Chikarmane, V ;

Heussner, R ;

Hussein, M ;

Hwang, J ;

Ingerly, D ;

James, R ;

Jeong, J ;

Kenyon, C ;

Lee, E ;

Lee, SH ;

Lindert, N ;

Liu, M ;

Ma, Z ;

Marieb, T ;

Murthy, A ;

Nagisetty, R ;

Natarajan, S ;

Neirynck, J ;

Ott, A ;

Parker, C ;

Sebastian, J ;

Shaheed, R ;

Sivakurnar, S ;

Steigerwald, J ;

Tyagi, S ;

Weber, C ;

Woolery, B ;

Yeoh, A ;

Zhang, K ;

Bohr, M .

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :657-660

[3] A deep sub-V, single power-supply SRAM cell with multi-VT, boosted storage node and dynamic load [J].

Itoh, K ;

Fridi, AR ;

Bellaouar, A ;

Elmasry, MI .

1996 SYMPOSIUM ON VLSI CIRCUITS - DIGEST OF TECHNICAL PAPERS, 1996, :132-133

[4] A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor [J].

Yamaoka, M ;

Shinozaki, Y ;

Maeda, N ;

Shimazaki, Y ;

Kato, K ;

Shimada, S ;

Yanagisawa, K ;

Osada, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (01) :186-194

[5] 0.4-v logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme [J].

Yamaoka, M ;

Osada, K ;

Ishibashi, K .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (06) :934-940

[6] A SRAM design on 65nm CMOS technology with integrated leakage reduction scheme [J].

Zhang, K ;

Bhattacharya, U ;

Chen, Z ;

Hamzaoglu, F ;

Murray, D ;

Vallepalli, N ;

Wang, Y ;

Zheng, B ;

Bohr, M .

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, :294-295

← 1 →