Performance Analysis of Dynamic Threshold MOS (DTMOS) Based 4-Input Multiplexer Switch for Low Power and High Speed FPGA Design

This paper presents a detailed performance analysis of a 4-input multiplexer switch based on two different dynamic threshold MOS (DTMOS) configurations. Proper and efficient sizing of all the required transistors in the design were done so as to achieve an improved performance in delay and optimum power delay product (PDP). As compared to minimum size DTMOS based multiplexer switch designs, augmenting transistor DTMOS and augmenting fixed reference voltage transistor DTMOS designs shows an improvement of 12.32% and 11.19% in delay as well as 8.29% and 8.26% in optimum power delay product (PDP) for Virtex-4 low cost 90 nm FPGA. Since FPGA consists of thousands of 4-input multiplexers in its design, so an improvement in delay and PDP will be of great significant for low power and high speed FPGA designs.