Partitioning Methods for Interface Circuit of Heterogeneous 3-D-ICs Under Process Variation

This paper presents the design of tier-to-tier interface circuits for 3-D-ICs, where different tiers may operate at different voltages and/or frequencies. The design and partitioning methodologies for the tier-to-tier interface circuit are discussed. The footprint, power, and performance of the interface are analyzed considering the effects of tier-to-tier process variations in 3-D-ICs and technology scaling. The simulation results show that dividing the interface circuit evenly between two tiers reduces footprint but increases power dissipation. For heterogeneous systems with different voltages for reading and writing tiers, dividing the interface between tiers provides better performance than the worst case scenario. On the other hand, placing the interface circuit in the reading tier maximizes throughput for a homogeneous system where both tiers operate at the same voltage. In advanced CMOS nodes, placing interface circuit in the reading tier is a better option due to high delay of the level shifters.