In-Memory Computing with Memristor Arrays

被引：0

作者：

Li, Can ^{[1
]}

Belkin, Daniel ^{[1
,4
]}

Li, Yunning ^{[1
]}

Yan, Peng ^{[1
,5
]}

Hu, Miao ^{[2
]}

Ge, Ning ^{[3
]}

Jiang, Hao ^{[1
]}

Montgomery, Eric ^{[2
]}

Lin, Peng ^{[1
]}

Wang, Zhongrui ^{[1
]}

Strachan, John Paul ^{[2
]}

Barnell, Mark ^{[6
]}

Wu, Qing ^{[6
]}

Williams, R. Stanley ^{[2
]}

Yang, J. Joshua ^{[1
]}

Xia, Qiangfei ^{[1
]}

机构：

[1] Univ Massachusetts, Amherst, MA 01003 USA

[2] Hewlett Packard Enterprise, Hewlett Packard Labs, Palo Alto, CA 94304 USA

[3] HP Inc, HP Labs, Palo Alto, CA 94304 USA

[4] Swarthmore Coll, Swarthmore, PA 19081 USA

[5] Huazhong Univ Sci & Technol, Wuhan Natl Lab Optoelect, Wuhan 430074, Hubei, Peoples R China

[6] US Air Force, Res Lab, Informat Directorate, Rome, NY 13441 USA

来源：

2018 IEEE 10TH INTERNATIONAL MEMORY WORKSHOP (IMW) | 2018年

关键词：

in-memory computing; memristor; RRAM; online learning; neural network; NETWORK;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Memristors with tunable non-volatile resistance states offer the potential for in-memory computing that mitigates the von-Neumann bottleneck. We build a large scale memristor array by integrating a transistor array with Ta/HfO2 memristors that have stable multilevel resistance states and linear IV characteristic. With off-chip peripheral driving circuits, the memristor chip is capable of high-precision analog computing and online learning. We demonstrate a weight-update scheme that provides linear and symmetric potentiation and depression with no more than two pulses for each cell. We train the array as a single-layer fully-connected feedforward neural network for the WDBC data base and achieve 98% classification accuracy. We further partition the array into a two-layer network, which achieves 91.71% classification accuracy for MNIST database experimentally. The system demonstrates high defect tolerance and excellent speed-energy efficiency.

引用

页码：161 / 164

页数：4