A low-power VLSI architecture for full-search block-matching motion estimation

被引：87

作者：

Do, VL ^{[1
]}

Yun, KY ^{[1
]}

机构：

[1] Univ Calif San Diego, Dept Elect & Comp Engn, La Jolla, CA 92093 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY | 1998年 / 8卷 / 04期

关键词：

full-search block matching; low power; VLSI motion estimation;

D O I：

10.1109/76.709406

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an architectural enhancement to reduce the power consumption Of the full-search block-matching (FSBM) motion estimation. Our approach is based on eliminating unnecessary computation using conservative approximation, Augmenting the estimation technique to a conventional systolic-architecture-based VLSI motion estimation reduces the power consumption by a factor of 2, while still preserving the optimal solution and the throughput. A register-transfer level implementation as welt as simulation results on benchmark video clips are presented.

引用

页码：393 / 398

页数：6

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