Chip-on-Board (CoB) technology for low temperature environments. Part I: Wire profile modeling in unencapsulated chips

被引：6

作者：

Jinka, K. K. ^{[1
]}

Ganesan, S.

Dasgupta, A.

Ling, S.

Shapiro, A.

Schatzel, D.

机构：

[1] Univ Maryland, CALCE Elect Prod & Syst Ctr, College Pk, MD 20742 USA

[2] Johns Hopkins Univ, Appl Phys Lab, Baltimore, MD 21218 USA

[3] NASA, Jet Propuls Lab, Pasadena, CA 91109 USA

来源：

MICROELECTRONICS RELIABILITY | 2007年 / 47卷 / 08期

基金：

美国国家航空航天局;

关键词：

D O I：

10.1016/j.microrel.2006.08.019

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An analytical model based on elastic strain energy minimization is developed for estimating the wire profile in unencapsulated ball wedge wire bond configuration for chip-on-board (CoB) technology. The wire profile is applicable to ball-wedge bonds with a height Off-set, and is modeled using a piece-wise continuous polynomial function (cubic spline) with appropriate boundary conditions at the two bond sites. Plastic deformation is ignored in the current analysis as a first-order approximation, since the interest is in parametric sensitivity studies. The model is useful for estimating the wire profile for different offset heights and wire spans, and serves as a starting point for subsequent thermornechanical stress analysis after encapsulation. Parametric studies are presented to explore the wire profile for different CoB geometries. (c) 2006 Elsevier Ltd. All rights reserved.

引用

页码：1246 / 1250

页数：5