An I/Q Channel 12-bit 200MS/s CMOS DAC with Three Stage Decoders for Wireless Communication

被引：0

作者：

Yu, Yunhua ^{[1
]}

Shi, Haitao ^{[1
]}

Ni, Weining ^{[2
]}

机构：

[1] China Univ Petr E China, Sch Informat & Control Engn, Dongying, Peoples R China

[2] Chinese Acad Sci, Inst Semicond, Beijing, Peoples R China

来源：

2009 INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS AND SIGNAL PROCESSING (WCSP 2009) | 2009年

关键词：

DAC; current-steering; CMOS mixed integrated circuit; Q(2) Random Walk;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a 12-bit 200 MHz CMOS DAC for wireless communication. The proposed DAC consists of a unit current-cell matrix for 6 MSBs and a unit current-cell matrix for 4 NSBs and a binary-weighted array for 2 LSBs. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q(2) random walk strategy. A voltage limiter circuit that limits the switching voltage magnitude is designed to reduce the coupling effect from the control signal to the load and improve the dynamic performance.

引用

页码：182 / +

页数：2

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