A High-Performance Sigma-Delta Modulator in 0.18μm CMOS Technology

被引:0
|
作者
Qian, Yingqi [1 ]
Zhang, Changchun
Liu, Zhongchao
Liu, Leilei
Luan, Yurong
Fang, Yuming
Guo, Yufeng
机构
[1] Nanjing Univ Posts & Telecommun, Jiangsu Prov Engn Lab RF Integrat & Microassembly, Nanjing 210023, Jiangsu, Peoples R China
来源
COMPUTER AND INFORMATION TECHNOLOGY | 2014年 / 519-520卷
基金
中国博士后科学基金; 中国国家自然科学基金;
关键词
Sigma-Delta (Sigma Delta) Modulator; Switched-Capacitor (SC) Integrator; Gain-boosted; Nonoverlapping Clock; GAIN;
D O I
10.4028/www.scientific.net/AMM.519-520.1085
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Sigma-Delta (Sigma Delta) modulators are commonly used in high-resolution analog-to-digital converters ( Cs). In this paper, a high-performance Sigma Delta modulator targeted for ultra-high-frequency (UHF) radio-frequency identification (RF ID) zero-intermediate frequency (ZIF) receivers is designed in standard 0.18pm CMOS technology. The modulator has been designed with switched-capacitor (SC) integrators employing gain-boosted operational amplifiers, voltage comparators and nonoverlapping clock generators to satisfy such requirements as high gain, low voltage and wide bandwidth. The behavioral-level modeling and circuit-level design are carried out with MATLAB/Simulink and Cadence/SpectreRF, respectively. Ultimately, the high-speed and low-power realization of a second-order single-bit modulator with an oversampling ratio (OSR) of 32 is presented. Simulation results shown that, from a I.8V supply, operated at a sampling frequency of 64MHz, a dynamic range of 53.4dB over a signal bandwidth of 1MHz is achieved.
引用
收藏
页码:1085 / +
页数:2
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