Providing Accountability in Heterogeneous Systems-on-Chip

被引:1
作者
Kalayappan, Rajshekar [1 ,2 ]
Sarangi, Smruti R. [2 ]
机构
[1] Indian Inst Technol Dharwad, Dharwad 580011, Karnataka, India
[2] Indian Inst Technol Delhi, New Delhi 110016, India
关键词
Accountability; auditing; SoC; third-party IPs; accelerators; heterogeneous processors;
D O I
10.1145/3241048
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
When modern systems-on-chip (SoCs), containing designs from different organizations, miscompute or underperform in the field, discerning the responsible component is a non-trivial task. A perfectly accountable system is one in which the on-chip component at fault is always unambiguously detected. The achievement of accountability can be greatly aided by the collection of runtime information that captures the events in the system that led to the error. Such information collection must be fair and impartial to all parties. In this article, we prove that logging messages communicated between components from different organizations is sufficient to provide accountability, provided the logs are authentic. We then construct a solution based on this premise, with an on-chip trusted auditing system to authenticate the logs. We present a thorough design of the auditing system, and demonstrate that its performance overhead is a mere 0.49%, and its area overhead is a mere 0.194% (in a heterogeneous 48 core, 400mm 2 chip). We also demonstrate the viability of this solution using three representative bugs found in popular commercial SoCs.
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页数:24
相关论文
共 26 条
  • [1] Abramovici M., 2009, CSIIRW
  • [2] Argyraki K., 2007, ICNP
  • [3] Backer Jerry, 2016, ACM T DES AUTOMAT EL, V22, P31
  • [4] Basu Kanad, 2011, IEEE VTS
  • [5] Bogdanov A., 2007, CHES
  • [6] Managing Trace Summaries to Minimize Stalls During Postsilicon Validation
    Chandran, Sandeep
    Panda, Preeti Ranjan
    Sarangi, Smruti R.
    Bhattacharyya, Ayan
    Chauhan, Deepak
    Kumar, Sharad
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25 (06) : 1881 - 1894
  • [7] Couillard B., 2002, U. S. Patent Application, Patent No. [09/ 774,599, 09774599]
  • [8] Goossens Kees, 2007, NOCS
  • [9] FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs
    Guin, Ujjwal
    Shi, Qihang
    Forte, Domenic
    Tehranipoor, Mark M.
    [J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2016, 21 (04)
  • [10] Hamalainen Panu, 2006, DSD