Spatially-Resolved Evaluation of Interface Defect Density on Macrostepped SiO2/SiC Using Local Deep Level Transient Spectroscopy

SiO2/SiC interfaces have been under intensive research, because the quality of the interfaces can significantly affect the performance and reliability of SiC power devices. For offering microscopic insights on the generation of interface defects, here we describe the application of our novel scanning probe microscopy method called local deep level transient spectroscopy (local DLTS) to a thermally oxidized Si-face 4H-SiC epitaxial layer. Our sample is an off-axially grown epitaxial layer which is intentionally modified to have wide flat terraces and macro-stepped features instead of typical terraces separated by atomic steps. A spatially resolved map of the interface defect density shows that the macro-steps have a significantly higher interface defect density than the wide flat terraces. The result suggests that high interface defect densities on typical off-axis SiO2/4H-SiC stacks might be related to the steps created during the step-controlled epitaxial growth. Local DLTS is useful for the microscopic evaluation of the interface quality.