Sizing consideration for leakage control transistor

被引：7

作者：

Farbiz, F ^{[1
]}

Farazian, M ^{[1
]}

Emadi, M ^{[1
]}

Sadeghi, K ^{[1
]}

机构：

[1] Univ Teheran, Dept Elect & Comp Engn, IC Design Lab, Tehran, Iran

来源：

17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA | 2004年

关键词：

D O I：

10.1109/ICVD.2004.1260992

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we report the use of the Genetic Algorithm (GA) to determine the optimum size of the leakage control transistor for low power applications. In the optimization, the energy-delay product is minimized The transistor is modeled by a neural network to increase the speed and the accuracy of the calculations.

引用

页码：639 / 641

页数：3