Identification of Faulty TSV with a Built-In Self-Test Mechanism

被引：16

作者：

Maity, Dilip Kumar ^{[1
]}

Roy, Surajit Kumar ^{[2
]}

Giri, Chandan ^{[2
]}

Rahaman, Hafizur ^{[2
]}

机构：

[1] Acad Technol, Dept Comp Sci & Engn, Adisaptagram, Hooghly, India

[2] Indian Inst Engn Sci & Technol, Dept Informat Technol, Sibpur, India

来源：

2018 IEEE 27TH ASIAN TEST SYMPOSIUM (ATS) | 2018年

关键词：

3D IC; Die; Post-bond test; TSV; BIST; DFT ARCHITECTURE; 3D-SICS;

D O I：

10.1109/ATS.2018.00012

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Three-dimensional Integrated Circuit (3D IC) based on through silicon via (TSV) has brought a drastic change in the IC technology. Since TSVs connect different layers of 3D stacks, their proper functioning is an essential prerequisite for the system operation. So, testing of TSV is essential for 3D IC. In this paper a cost-effective Built-in Self-Test (BIST) mechanism is proposed for the post-bond test of TSVs in 3D ICs. The test method aims at identifying single and multiple defective TSVs using low test time with minimum hardware. The time cycle needed for testing is calculated and is compared with previous proposed methods. The simulation result shows that the proposed BIST circuit is beneficial over prior BIST technology in terms of test time cycle and hardware requirement.

引用

页码：1 / 6

页数：6