On the correctness of hardware scheduling mechanisms for out-of-order execution

被引：0

作者：

Mueller, SM ^{[1
]}

Paul, WJ ^{[1
]}

机构：

[1] Univ Saarland, Dept Comp Sci 14, D-66123 Saarbrucken, Germany

来源：

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 1998年 / 8卷 / 02期

关键词：

D O I：

10.1142/S0218126698000134

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Hardware scheduling mechanisms are commonly used in current processors in order to make better use of instruction level parallelism. So far, such a mechanism is considered to be correct, if it avoids the standard structural and data hazards. However, based on two classical scheduling mechanisms, it will be shown that this condition is neither sufficient nor necessary for the correctness of such a mechanism, and that deadlocks are a serious matter in out-of-order execution as well. In addition, the paper provides sufficient conditions for the correctness of scheduling mechanisms.

引用

页码：301 / 314

页数：14

共 12 条

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