A limit cycle suppressing arithmetic format for digital filters

被引：3

作者：

Bauer, PH ^{[1
]}

Ralev, KR ^{[1
]}

机构：

[1] Univ Notre Dame, Dept Elect Engn, Lab Image & Signal Anal, Notre Dame, IN 46556 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 1998年 / 45卷 / 10期

关键词：

block floating point arithmetic; limit cycles; overflow oscillations;

D O I：

10.1109/81.728865

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper it will be shown that any digital filter with a stable transfer function can be implemented free of limit cycles, if block floating point arithmetic is used in conjunction with the so-called exponent saturation and flush-to-zero option. A certain system dependent minimum block mantissa length is required. Limit cycle suppression is achievable regardless of the structure and the quantization format. This format is simple to implement even on fixed point processors and offers high dynamic range.

引用

页码：1104 / 1107

页数：4

共 11 条

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