Algorithm and Architecture for Quarter Pixel Motion Estimation for H.264/AVC

被引：0

作者：

Chatterjee, Sumit K. ^{[1
]}

Chakrabarti, Indrajit ^{[1
]}

机构：

[1] IIT Kharagpur, Dept E & ECE, Kharagpur, W Bengal, India

来源：

2013 FOURTH NATIONAL CONFERENCE ON COMPUTER VISION, PATTERN RECOGNITION, IMAGE PROCESSING AND GRAPHICS (NCVPRIPG) | 2013年

关键词：

fast motion estimation algorithm; low power VLSI design; motion estimation; memory access; quarter pixel;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The present paper proposes a fast algorithm and its VLSI architecture for fast quarter pixel (QP) accurate motion estimation (ME). The proposed algorithm is based on the distribution of the QP motion vectors (MVs) around the half pixel MV. The proposed algorithm efficiently explores the most likely QP locations and therefore skips the unlikely ones. The number of QP search locations for the proposed algorithm is reduced by 50% compared to the original full search method but results in only about 0.12 dB peak signal to noise ratio degradation. The VLSI architecture of the proposed algorithm theoretically can process thirty three 1280x720 HDTV frames per second. The power consumption of the proposed architecture is also reduced by 15% compared to a recently reported architecture.

引用

页数：4

共 5 条

[1] Bo Zhou, 2003, Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits, and Systems (IEEE Cat. No.03EX749), P611
[2] Chatterjee S. K., P IMPACT 2009, P206
[3] Low-power VLSI design for motion estimation using adaptive pixel truncation
He, ZL
Tsui, CY
Chan, KK
Liou, ML
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2000, 10 (05) : 669 - 678
[4] Oktem S., 2007, P 10 IEEE DSD
[5] A fast algorithm and its VLSI architecture for fractional motion estimation for H.264/MPEG-4 AVC video coding
Wang, Yu-Jen
Cheng, Chao-Chung
Chang, Tian-Sheuan
[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2007, 17 (05) : 578 - 583

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