Optimal Cell Design for Enhancing Reliability Characteristics for sub 30 nm NAND Flash Memory

被引：2

作者：

Cho, Eun Suk ^{[1
]}

Kim, Hyun Jung ^{[1
]}

Kim, Byoung Taek ^{[1
]}

Song, Jai Hyuk ^{[1
]}

Song, Du Heon ^{[1
]}

Choi, Jeong-Hyuk ^{[1
]}

Suh, Kang-Deog ^{[2
]}

Chung, Chilhee ^{[1
]}

机构：

[1] Samsung Elect Co, Semicond Business Div, NAND Flash Proc Architecture Team, San 24, Yongin 446711, Gyunggi Do, South Korea

[2] Sungkyunkwan Univ, Sch Informat & Commun Engn, Suwon 440746, South Korea

来源：

2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM | 2010年

关键词：

Reliability; SCE; Coupling Rario; Floating Gate; NAND Flash; INTERFERENCE;

D O I：

10.1109/IRPS.2010.5488763

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

One of the critical scaling barriers in sub 30 nm NAND Flash technology node is an abrupt threshold voltage drop of cell transistors by short channel effect. It increases program voltage which leads, in turn, to fatal reliability issues. A simple way to relieve the short channel effect is increasing the channel boron concentration. However it degrades endurance characteristics by deteriorating boosting efficiency on inhibit operation. In this paper, we present an optimal cell design for the improved reliability characteristics in the level of mass production for the future NAND Flash with floating gate cells.

引用

页码：611 / 614

页数：4

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