A 12-GS/s81-mW 5-bit Time-Interleaved Flash ADC with Background Timing Skew Calibration

被引：27

作者：

El-Chammas, Manar ^{[1
]}

Murmann, Boris ^{[1
]}

机构：

[1] Stanford Univ, Stanford, CA 94305 USA

来源：

2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2010年

关键词：

A/D conversion; time-interleaving; calibration;

D O I：

10.1109/VLSIC.2010.5560315

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 12-GS/s 5-bit time-interleaved flash ADC is realized in 65-nm CMOS. The design utilizes a background timing skew calibration technique to improve dynamic performance, and comparator offset calibration to reduce power dissipation. The experimental prototype achieves an SNDR of 25.1 dB at Nyquist and 27.5 dB for low frequency inputs. The circuit occupies an active area of 0.44 mm(2) and consumes 81 mW from a 1.1-V supply.

引用

页码：157 / 158

页数：2