We show damage during high density (similar to 10(11)cm(-3)) ICP metal etch to occur exclusively during clearing of the metal (endpoint). With an increase of the chamber height to 8 cm, we demonstrate negligible stress to 60A devices. The significant changes as indicated by modeling that lead to lower damage are decrease in ion/electron density as well as the electric field near the wafer surface. However, for thinner oxides of 45 and 35A gates, we show a re-emergence of damage based on Vt shift (similar to 150 mV) of PMOS devices induced by the plasma stress. Despite no observable Vt shift in the NMOSFETs, we have uncovered degradation of interface states using charge pumping measurements. We report here for the first time observation of a latent antenna effect wherein the antenna effect of a metal conductor is raised to that of the surrounding geometry. This paper also addresses, the effect of chamber condition, polarity of charging, damage mechanism and its impact on reliability.