A Digital-Intensive 2-to-9.2 Gb/s/pin Memory Controller I/O with Fast-Response LDO in 10nm CMOS

被引：0

作者：

Inti, Rajesh ^{[1
]}

Mansuri, Mozhgan ^{[1
]}

Kennedy, Joe ^{[1
]}

Venkatram, Hariprasath ^{[1
]}

Hsu, Chun-Ming ^{[1
]}

Martin, Aaron ^{[1
]}

Jaussi, James ^{[1
]}

Casper, Bryan ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

来源：

2018 IEEE SYMPOSIUM ON VLSI CIRCUITS | 2018年

关键词：

LPDDR5; transceiver; DFE; clock; LDO; ADDLL;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The proposed digital-intensive LPDDR5 I/O architecture operates from 2 to 9.2Gb/s. The LDO-based ADDLL operates at 1-5GHz with >= 14dB PSRR. Fast-response LDO enhanced with feed-forward (FF) path enables rapid power state transitions with minimal degradation in eye timing margin. The digital device-only TX supports 30-50 Omega ODT, 100-300mV(pp), single ended output swing and a 2-tap FFE. The bias-free clocked-latch RX uses switched current DACs to implement a 2-tap DFE.

引用

页码：151 / 152

页数：2