A Frequency Agile Synthesizer Using DDS and PLL Techniques for FMCW Radar

被引:0
作者
Zhu, Yingshen [1 ]
Zhang, Hui [1 ]
Hong, Wei [1 ]
机构
[1] Southeast Univ, Sch Informat Sci & Engn, State Key Lab Millimeter Waves, Nanjing 210096, Jiangsu, Peoples R China
来源
2015 ASIA-PACIFIC MICROWAVE CONFERENCE (APMC), VOLS 1-3 | 2015年
关键词
FMCW; DDS; PLL; RADAR;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A frequency synthesizer using phase-locked loop (PLL) and direct digital synthesis (DDS) techniques for frequency modulated continuous-wave (FMCW) radar which has low phase noise is presented. Fast switching time and narrow channel spacing can be achieved by DDS. The modulation width of 850MHz, from 12.6GHz to 13.45GHz, is achieved. The phase noise of 13.4GHz frequency synthesizer at 1 MHz offset is 118.34dBc/Hz, the reference spur is better than-69dBc and the output power is over-3dBm.
引用
收藏
页数:3
相关论文
共 50 条
  • [41] Contactless Human Respiratory Frequency Monitoring System Based on FMCW Radar
    Erdyarahman, Rayhan
    Suratman, Fiky Y.
    Pramudita, A. A.
    2022 IEEE ASIA PACIFIC CONFERENCE ON WIRELESS AND MOBILE (APWIMOB), 2022, : 83 - 89
  • [42] Implementation of FMCW RADAR using FPGA
    Bhise, Priyanka
    Chopade, N. B.
    Rajkumar
    2017 INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION, CONTROL AND AUTOMATION (ICCUBEA), 2017,
  • [43] Modern frequency estimation algorithms for FMCW radar systems
    Pichler, M
    Stelzer, A
    Fischer, A
    Gulden, P
    Weigel, R
    TESTING, RELIABILITY, AND APPLICATION OF MICRO- AND NANO-MATERIAL SYSTEMS, 2003, 5045 : 223 - 229
  • [44] Low Complexity Frequency Offset Estimation for FMCW Radar
    Lee, Jinyong
    Lee, Jingu
    Kim, Youngseh
    Kim, Kanghoon
    Kim, Younglok
    PROCEEDINGS OF THE 2ND INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTER SCIENCE AND ENGINEERING (CSE 2013), 2013, 42 : 303 - 306
  • [45] Comparing Baseband and Intermediate Frequency FMCW Radar Receivers
    Meyer, Bernard
    de Swardt, Johann B.
    van der Merwe, Paul
    2017 IEEE AFRICON, 2017, : 563 - 568
  • [46] Design of Low Power, High Speed PLL Frequency Synthesizer using Dynamic CMOS VLSI Technology
    Nirmalraj, T.
    Radhakrishnan, S.
    Karn, Rakesh Kumar
    Pandiyan, S. K.
    2017 IEEE INTERNATIONAL CONFERENCE ON POWER, CONTROL, SIGNALS AND INSTRUMENTATION ENGINEERING (ICPCSI), 2017, : 1074 - 1076
  • [47] A High-Linear PLL-based FMCW Frequency Synthesizer with 42kHz rms FM Error and 1.2-GHz Chirp Bandwidth
    Zhang, Zitong
    Lu, Yuri
    Wu, Xiaoyuan
    Deng, Hao
    Shi, Chunqi
    Huang, Leilei
    Chen, Jinghong
    Zhang, Runxi
    IEICE ELECTRONICS EXPRESS, 2024,
  • [48] A High-Linear PLL-based FMCW Frequency Synthesizer with 42-kHz rms FM Error and 1.2-GHz Chirp Bandwidth
    Zhang, Zitong
    Lu, Yuri
    Wu, Xiaoyuan
    Deng, Hao
    Shi, Chunqi
    Huang, Leilei
    Chen, Jinghong
    Zhang, Runxi
    2024 IEEE WIRELESS AND MICROWAVE TECHNOLOGY CONFERENCE, WAMICON, 2024,
  • [49] A high-linear PLL-based FMCW frequency synthesizer with 42-kHz rms FM error and 1.2-GHz chirp bandwidth
    Zhang, Zitong
    Lu, Yuri
    Wu, Xiaoyuan
    Deng, Hao
    Shi, Chunqi
    Huang, Leilei
    Chen, Jinghong
    Zhang, Runxi
    IEICE ELECTRONICS EXPRESS, 2024, 21 (10):
  • [50] Design of Low-Noise X-band Frequency Source Based on DDS-PLL
    Yao, Peidong
    Xu, Leijun
    Sun, Zhenhua
    2020 IEEE 2ND INTERNATIONAL CONFERENCE ON CIRCUITS AND SYSTEMS (ICCS 2020), 2020, : 11 - 14