A High-Precision Low-Area Unified Architecture for Lossy and Lossless 3D Multi-Level Discrete Wavelet Transform

This paper presents a high-precision low area lifting-based architecture for the unified implementation of both lossy and lossless 3D multi-level discrete wavelet transform (DWT) using LeGall 5/3 wavelet and cohen-daubechies-feauveau 9/7 wavelet. The proposed system is parallel-pipelined, and resource is shared between the lossy and lossless modes, producing a throughput of two outputs/clock and achieving a high-speed and low-area solution. The data width of the design is taken as 20 bits to reach a high peak signal-to-noise-ratio value for multi-level 3D DWT. Targeting a portable and real-time solution, the proposed architecture was successfully implemented on Xilinx Virtex-5 series field programmable gate array, achieving a clock speed of 290 MHz with a power consumption of 467 mW at 200 MHz clock frequency. The design has also been implemented in UMC 90 nm CMOS technology, which consumes 329 mW power at 200 MHz clock frequency. The proposed solution may be configured as lossless or lossy compression, in the field of 3D image compression system, according to the necessity of the user.