A process variation compensating technique for sub-90nm dynamic circuits

被引：28

作者：

Kim, CH ^{[1
]}

Roy, K ^{[1
]}

Hsu, S ^{[1
]}

Alvandpour, A ^{[1
]}

Krishnamurthy, RK ^{[1
]}

Borkar, S ^{[1
]}

机构：

[1] Purdue Univ, Dept ECE, W Lafayette, IN 47906 USA

来源：

2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2003年

关键词：

D O I：

10.1109/VLSIC.2003.1221203

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A process variation compensating technique for dynamic circuits is described for sub-90nm technologies where leakage variation is severe. A keeper whose effective strength is optimally programmable based on die leakage enables 10% faster performance, 35% reduction in delay variation, and 5x reduction in robustness failing dies over conventional static keeper design in 90nm dual-V-t CMOS.

引用

页码：205 / 206

页数：2

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