Stress dependent degradation mechanisms on commercially available GaN Normally-Off transistors

In this paper, a series of stress test experiments were carried out on GaN Normally-Off COTS transistors (eGaN-on-Si) accelerating the normal degradation process through the use of elevated temperature and biasing conditions. The primary objective is to build a predictive model of the reliability of such GaN electronic components used in power conversion. The experiments were performed on 80 samples allocated in: i) four conditions of DC off-state and on-pulsed step stress sequences, ii) three high temperature off-state endurance lifetest sequences, iii) and three on-pulsed lifetest sequences. These series of high temperature step stress and lifetest conditions allow to identify and separate the infant mortality from the random to wear-out mechanisms occurring in accelerated DC off state, forward-gate and pulsed high current drain testing. Eyring model was determined based on Weibull plot data analysis allowing to quantify a wearout failure mechanism consisting in the shortening of the gate junction. The n factor of the inverse power law of the off-state voltage at 150 degrees C channel was determined to be 7. On-pulsed experiments carried out at Ids(pulse) = 16A for 3 junction temperatures demonstrated Rds(on) degradation and an activation energy of 1.28 eV (failure criteria 50% drift on Idson(max)).