Design procedure for settling time minimization in three-stage nested-miller amplifiers

被引：34

作者：

Pugliese, Andrea ^{[1
]}

Cappuccino, Gregorio ^{[1
]}

Cocorullo, Giuseppe ^{[1
]}

机构：

[1] Univ Calabria, Dept Elect Comp Sci & Syst, I-87036 Arcavacata Di Rende, Italy

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2008年 / 55卷 / 01期

关键词：

analog design; frequency compensation; operational amplifiers (op-amps); transient response;

D O I：

10.1109/TCSII.2007.906086

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Low-power, low-voltage, and high-performance requirements are badly needed for operational amplifiers (op-amps) in modern applications. In this brief, a design method for minimizing the settling time in three-stage nested-Miller schemes is presented. As an application example, a CMOS 0.35-mu m voltage follower with 115-dB dc gain and fastest step response to 1% accuracy level, is designed. Circuital simulations demonstrate that the proposed procedure allows the amplifier settling-time/power-consumption ratio to be significantly improved with respect to conventionally designed op-amps.

引用

页码：1 / 5

页数：5

共 15 条

[1] Design procedures for three-stage CMOS OTAs with nested-Miller compensation [J].

Cannizzaro, Salvatore Omar ;

Grasso, Alfio Dario ;

Mita, Rosario ;

Palumbo, Gaetano ;

Pennisi, Salvatore .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2007, 54 (05) :933-940

[2]

Eschauzier RGH., 1995, Frequency Compensation Techniques for Low-Power Operational Amplifiers

[3]

FAN X, 2003, IEEE J SOLID-ST CIRC, V38, P1735

[4] Improved reversed nested Miller frequency compensation technique with voltage buffer and resistor [J].

Grasso, Alfio Dario ;

Marano, Davide ;

Palumbo, Gaetano ;

Pennisi, Salvatore .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54 (05) :382-386

[5] Three-stage CMOS OTA for large capacitive loads with efficient frequency compensation scheme [J].

Grasso, Alfio Dario ;

Palumbo, Gaetano ;

Pennisi, Salvatore .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2006, 53 (10) :1044-1048

[6] RELATIONSHIP BETWEEN FREQUENCY-RESPONSE AND SETTLING TIME OF OPERATIONAL AMPLIFIERS [J].

KAMATH, BY ;

MEYER, RG ;

GRAY, PR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (06) :347-352

[7] Analysis of multistage amplifier-frequency compensation [J].

Leung, K.N. ;

Mok, P.K.T. .

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 2001, 48 (09) :1041-1056

[8]

MARQUES A, 1998, P IEEE INT C EL CIRC, V2, P505

[9] Design methodology and advances in nested-miller compensation [J].

Palumbo, G ;

Pennisi, S .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 2002, 49 (07) :893-903

[10]

Palumbo G., 2002, Feedback Amplifiers: Theory and Design

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