An 80 MHz PLL with 72.7 ps peak-to-peak jitter

This paper presents a design of a 72.7ps peak-to-peak (p2p) jitter, 80 MHz, phase-locked loop (PLL) circuit for digital video broadcasting over terrestrial (DVB-T) receivers. A step-down voltage regulator is utilized to suppress the coupled supply noise. A zero offset charge pump is employed to eliminate the static phase offset caused by the charge offset when the PLL is in lock. The measurement results on silicon using the TSMC (Taiwan Semiconductor Manufacturing Company) 0.35 mu m 2P4M CMOS process show that the proposed PLL achieves as low as 72.7 ps p2p jitter on silicon when the output frequency is 80 MHz and the power consumption is merely 10. 5 mW given a 3.3 V power supply. (C) 2007 Elsevier Ltd. All rights reserved.