HyPaFilter plus : Enhanced Hybrid Packet Filtering Using Hardware Assisted Classification and Header Space Analysis

被引:19
|
作者
Fiessler, Andreas [1 ]
Lorenz, Claas [1 ]
Hager, Sven [2 ]
Scheuermann, Bjoern [2 ]
Moore, Andrew W. [3 ]
机构
[1] Genua GmbH, D-85551 Kirchheim, Germany
[2] Humboldt Univ, Dept Comp Engn, D-12489 Berlin, Germany
[3] Univ Cambridge, Comp Lab, Cambridge CB3 0FD, England
关键词
Packet classification; FPGA hardware accelerator; firewall; header space analysis;
D O I
10.1109/TNET.2017.2749699
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Firewalls, key components for secured network infrastructures, are faced with two different kinds of challenges: first, they must be fast enough to classify network packets at line speed, and second, their packet processing capabilities should be versatile in order to support complex filtering policies. Unfortunately, most existing classification systems do not qualify equally well for both requirements: systems built on special-purpose hardware are fast, but limited in their filtering functionality. In contrast, software filters provide powerful matching semantics, but struggle to meet line speed. This motivates the combination of parallel, yet complexity-limited specialized circuitry with a slower, but versatile software firewall. The key challenge in such a design arises from the dependencies between classification rules due to their relative priorities within the rule set: complex rules requiring software-based processing may be interleaved at arbitrary positions between those where hardware processing is feasible. Therefore, we discuss approaches for partitioning and transforming rule sets for hybrid packet processing. As a result, we propose HyPaFilter+, a hybrid classification system consisting of an FPGA-based hardware matcher and a Linux netfilter firewall, which provides a simple, yet effective hardware/software packet shunting algorithm. Our evaluation shows up to 30-fold throughput gains over software packet processing.
引用
收藏
页码:3655 / 3669
页数:15
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