A high-resolution multi-phase delay-locked loop with offset locking technique

In this work, we propose a new type of high-resolution delay-locked loop (DLL) which achieves the performance of high-resolution output by offset locking techniques without restrictions of intrinsic delay in the delay cell. Compared to traditional multi-phase clock generator, this architecture has the features of small size, low jitters, low-power consumption and high resolution. This DLL has been fabricated in 0.35m complementary metal-oxide-semiconductor (CMOS) process. The measured root-mean-square and peak-to-peak jitters are 2.89ps and 31.1ps at 250MHz, respectively. The power dissipation is 68mW for a supply voltage of 3.3V. The maximum resolution of this work is 144p and the intrinsic delay of 0.35m CMOS process is 220ps. Comparing with intrinsic delay, the improvement of maximum resolution is 34.5%.