Non-Planar, Multi-Gate InGaAs Quantum Well Field Effect Transistors with High-K Gate Dielectric and Ultra-Scaled Gate-to-Drain/Gate-to-Source Separation for Low Power Logic Applications

被引:0
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作者
Radosavljevic, M. [1 ]
Dewey, G. [1 ]
Fastenau, J. M. [2 ]
Kavalieros, J. [1 ]
Kotlyar, R. [1 ]
Chu-Kung, B. [1 ]
Liu, W. K. [2 ]
Lubyshev, D. [2 ]
Metz, M. [1 ]
Millard, K. [1 ]
Mukherjee, N. [1 ]
Pan, L. [1 ]
Pillarisetty, R. [1 ]
Rachmady, W. [1 ]
Shah, U. [1 ]
Chau, Robert [1 ]
机构
[1] Intel Corp, Technol & Mfg Grp, Hillsboro, OR 97124 USA
[2] IQE Inc, Bethlehem, PA 18015 USA
来源
2010 INTERNATIONAL ELECTRON DEVICES MEETING - TECHNICAL DIGEST | 2010年
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中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, non-planar, multi-gate InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations (L-SIDE) of 5nm are reported for the first time. The high-K gate dielectric formed on this non-planar device structure has the expected thin T-OXE of 20.5 angstrom with low J(G), and high quality gate dielectric interface. The simplified S/D scheme is needed for the non-planar architecture while achieving significant reduction in parasitic resistance. Compared to the planar high-K InGaAs QWFET with similar T-OXE, the non-planar, multi-gate InGaAs QWFET shows significantly improved electrostatics due to better gate control. The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III-V QWFETs for low power logic applications.
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页数:4
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