Enhanced Critical Electrical Characteristics in a Nanoscale Low-Voltage SOI MOSFET With Dual Tunnel Diode

被引：23

作者：

Anvarifard, Mohammad Kazem ^{[1
]}

Orouji, Ali Asghar ^{[1
]}

机构：

[1] Semnan Univ, Dept Elect & Comp Engn, Semnan 3513119111, Iran

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2015年 / 62卷 / 05期

关键词：

Dual tunnel diode (DTD); floating body effect (FBE); kink effect; L-shaped trench; partially depleted silicon-on-insulator MOSFET (PD-SOI MOSFET);

D O I：

10.1109/TED.2015.2414825

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief presents a nanoscale low-voltage partially depleted silicon-on-insulator (SOI) structure with improved electrical performance. The brain of the proposed structure is a dual tunnel diode (DTD) composed of a heavily doped p-type L-shaped trench. The accumulated holes are effectively released by the tunnel current of DTD, thus reducing the critical kink effect. Compared with a conventional SOI, the proposed structure is considered as an efficient rival in nanoscale-integrated applications.

引用

页码：1672 / 1676

页数：5

共 17 条

[1] A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs [J].

Abbasi, Abdollah ;

Orouji, Ali A. .

MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2013, 16 (06) :1821-1827

[2] Compact Modeling of Partially Depleted Silicon-on-Insulator Drain-Extended MOSFET (DEMOSFET) Including High-Voltage and Floating-Body Effects [J].

Agarwal, Tarun Kumar ;

Trivedi, Amit Ranjan ;

Subramanian, Vaidyanathan ;

Kumar, M. Jagadesh .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (10) :3485-3493

[3]

[Anonymous], 2012, ATLAS US MAN 2 D DEV

[4]

Colinge J.-P., 2004, SILICON ON INSULATOR, V3rd

[5]

Ernst T, 1999, ELEC SOC S, V99, P329

[6]

Kedzierski J., 2003, IEDM M

[7] High-Performance Partially Depleted SOI PFETs With In Situ Doped SiGe Raised Source/Drain and Implant-Free Extension [J].

Khakifirooz, Ali ;

Cheng, Kangguo ;

Cai, Jin ;

Kimball, Anne ;

Kulkarni, Pranita ;

Reznicek, Alexander ;

Adam, Thomas ;

Edge, Lisa ;

Bu, Huiming ;

Doris, Bruce ;

Shahidi, Ghavam .

IEEE ELECTRON DEVICE LETTERS, 2011, 32 (03) :267-269

[8] Body-contacted SOI MOSFET structure with fully bulk CMOS compatible layout and process [J].

Koh, YH ;

Choi, JH ;

Nam, MH ;

Yang, JW .

IEEE ELECTRON DEVICE LETTERS, 1997, 18 (03) :102-104

[9] Improvement of RF Performance by Using Tunnel Diode Body Contact Structure in PD SOI nMOSFETs [J].

Lu, Kai ;

Chen, Jing ;

Luo, Jiexin ;

Liu, Jun ;

Wu, Qingqing ;

Chai, Zhan ;

Wang, Xi .

IEEE ELECTRON DEVICE LETTERS, 2014, 35 (01) :15-17

[10] Temperature Dependence of Hysteresis Effect in Partially Depleted Silicon-on-Insulator MOSFETs [J].

Luo, Jiexin ;

Chen, Jing ;

Zhou, Jianhua ;

Wu, Qingqing ;

Chai, Zhan ;

Wang, Xi .

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2012, 12 (01) :63-67

← 1 2 →