Analytical modeling of the gate tunneling leakage for the determination of adequate high-k dielectrics in double-gate SOI MOSFETs at the 22 nm node

被引：17

作者：

Darbandy, Ghader

Ritzenthaler, Romain

Lime, Francois

Garduno, Ivan ^{[1
]}

Estrada, Magali ^{[1
]}

Cerdeira, Antonio ^{[1
]}

Iniguez, Benjamin

机构：

[1] CINVESTAV IPN, Depto Ingn Elect, Secc Elect Estado Solido, Mexico City, DF, Mexico

来源：

SOLID-STATE ELECTRONICS | 2010年 / 54卷 / 10期

关键词：

Compact analytical model; High-k dielectrics; Gate leakage current; Direct tunneling; SILICON; CURRENTS; VOLTAGE; CMOS;

D O I：

10.1016/j.sse.2010.06.015

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the gate leakage current in metal-oxide-semiconductor (MOS) junctions/devices/or transistors is modeled and studied in order to find promising materials for double-gate (DG) MOSFETs at 22 nm node by considering analytical models of the direct tunneling current (based on a proper calculation of the WKB tunneling probability in the gate oxide). We present a theoretical study to find the most promising gate oxide materials for the 22 nm technological node with the predicted maximum value of leakage current (10(-2) A/cm(2)) that is tolerable for that node, according to the ITRS roadmap. The effects of electron effective mass, dielectric constant k-value and barrier height on the Delta E-c-k permitted values have been studied. (C) 2010 Elsevier Ltd. All rights reserved.

引用

页码：1083 / 1087

页数：5

共 25 条

[1] Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs [J].