A fast digit based Montgomery multiplier designed for FPGAs with DSP resources

A fast Montgomery multiplier design utilizing the DSP resources in modem FPGAs is presented. In the proposed design, the operand size is the multiples of 528 bits and the digit size is 48 bits. The design has 48 x 48 bit digit multipliers built from the DSP slices performing 24 x 16 bit multiplications and a carry select accumulator built from the DSP slices performing 48 bit additions. The proposed Montgomery multiplier works iteratively. In each iteration, a digit of an operand is multiplied by the digits of the other, the result is accumulated, and reduced by Montgomery method. An iteration takes not one but eight cycles to keep the digit multiplier count low and save some hardware resources. The proposed design is implemented for Virtex-7 FPGAs. The performance results are comparable with the best results in the literature. Substantial savings in FPGA logic resources are obtained.