A 1-V 5-bit 0.5 GS/s time-based flash ADC in 0.18 μm CMOS technology

A novel low-voltage rail-to-rail parallel time-based analog-to-digital converter (ADC) is proposed. The proposed ADC works like a conventional flash ADC except that the process is performed in the time-domain. Since the operation of analog integrated circuits at low supply voltages is limited, converting the voltage signals to the time domain improves the efficiency of the circuit. In this paper, a constant-delay ladder is utilized to make the reference delay-times to compare with the input signal. A 1-V 5-bit 500 MS/s ADC has been designed and simulated in 0.18 mu m CMOS technology consumed 3.66 mW. The simulation results show 0.3lsb and 0.2lsb for INL and DNL respectively. Signal-to-noise and distortion ratio (SNDR) of the proposed ADC is 26.7 dB at Nyquist frequency. The rail-to-rail operation and linearity of the voltage-to-time converter (VTC) improved the efficiency of the ADC comparing to the similar time-based ADCs. The figure-of-merit (FoM) of the ADC is about 0.31 (pJ/conv.step).