Optimizing resource utilization in system-on-a-programmable-chip with location-aware genetic algorithm

This paper presents a static task scheduling using genetic algorithm technique to task systems whose targeted execution environment is comprised of finite amounts of reconfigurable hardware. This scheduling algorithm is built upon previous work [1-3]. In this paper, the algorithm has been expanded to include a feature to allocate tasks to specific functional units. Reconfigurable hardware is characterized by the fact that its structure and logical functionality can be altered any time after the hardware devices are constructed. Such an environment is assumed to allow for the use of multiple sequential processing elements (intellectual processors such as Xilinx MicroBlaze or Altera Nios-II), task-specific logic (application specific hardware) and a communication network within the reconfigurable hardware. Such a system is called system-on-a-programmable-chip (SoPC). The goal of this strategy is to create a system specification (or schedule) that has minimal overall execution time under the constraint that the implementation of such schedules do not require more resources of any type than is present within the reconfigurable hardware.